Implementation of high-speed–low-power adaptive finite impulse response filter with novel architecture

Abstract

An energy efficient high-speed adaptive finite impulse response filter with novel architecture is developed. Synthesis results along with novel architecture on different complementary metal–oxide semiconductor (CMOS) families are presented. Analysis is performed using Artix-7, Spartan-6 and Virtex-4 for most popular adaptive least mean square filter for different orders such as N = 8, 16, 32. The presented work is done using MATLAB (2013b) and Xilinx (14.2). From the synthesis results, it can be found that CMOS (28 nm) achieves the lowest power and critical path delay compared to others, and thus proves its efficiency in terms of energy. Different parameters are considered such as look up tables and input–output blocks, along with their optimised results.

Keywords

• FIR filters
• CMOS digital integrated circuits
• adaptive filters
• integrated circuit design
• low-power electronics
• high-speed-low-power adaptive finite impulse response filter
• energy efficient high-speed adaptive finite impulse response filter
• complementary metal-oxide semiconductor
• CMOS family
• Artix-7
• Spartan-6
• Vertex-4
• adaptive least mean square filter
• Matlab
• Xilinx
• critical path delay
• size 28 nm