Spike-RISC: Algorithm/ISA Co-Optimization for Efficient SNNs on RISC-V

Abstract

Artificial intelligence has proven its benefits in many domains. Yet, traditional deep learning models are still too energy and compute-intensive for resource-constrained edge environments. Spiking neural networks (SNNs) promise a more energy-efficient and low-latency alternative to traditional neural networks. However, their leaky-integrate and fire (LIF) neurons rely on complex floating-point equations, which are very costly in embedded systems. Further, many computations are unnecessary because SNNs are inherently sparse. This paper proposes Spike-RISC, a holistic algorithm/instruction set architecture (ISA) co-optimization for efficient SNN inference. Our key algorithm optimizations include quantizing the weights to just eight bits and exploiting the network’s sparsity in hardware and software. We enhance the ISA of a RISC-V processor to accelerate two core SNN operations during inference. The sparsity-aware vector unit processes the fully connected layers avoiding unnecessary computations. Additionally, we implement custom vector instructions for LIF neurons. Compared to the floating-point baseline, our Spike-RISC improves energy efficiency by 108 x and reduces latency by 113 x, making SNNs compatible with resource-constrained edge environments.

Keywords

• Spiking neural networks
• edge AI
• RISC-V
• domain-specific accelerators