Inverse design and characterization of compact, broadband, and low-loss chip-scale photonic power splitters

Abstract

The scalability of integrated photonics hinges on low-loss chip-scale components, which are important for classical applications and crucial in the quantum domain. An important component is the power splitter, which is an essential building block for interferometric devices. Here, we use inverse design by topology optimization to devise a generic design framework for developing power splitters in any material platform, although we focus the present work on silicon photonics. We report on the design, fabrication, and characterization of silicon power splitters and explore varying domain sizes and wavelength spans around a center wavelength of 1550 nm. This results in a set of power splitters tailored for ridge, suspended, and embedded silicon waveguides with an emphasis on compact size and wide bandwidths. The resulting designs have a footprint of $2\,\mu\textrm{m}\times3\,\mu\textrm{m}$ and exhibit remarkable 0.5 dB bandwidths exceeding 300 nm for the ridge and suspended power splitters and 600 nm for the embedded power splitter. We fabricate the power splitters in suspended silicon circuits and characterize the resulting devices using a cutback method. The experiments confirm the low excess loss, and we measure a 0.5 dB bandwidth of at least 245 nm—limited by the wavelength range of our lasers.

Keywords

• inverse design
• topology optimization
• photonic integrated circuits
• power splitter