IEEE Access (Jan 2023)

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

  • V. Bharath Sreenivasulu,
  • Aruna Kumari Neelam,
  • Sekhar Reddy Kola,
  • Jawar Singh,
  • Yiming Li

DOI
https://doi.org/10.1109/ACCESS.2023.3306050
Journal volume & issue
Vol. 11
pp. 90421 – 90429

Abstract

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In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In JL mode, the ON current ( $I_{\mathrm {ON}}$ ) rises with an increase in temperature compared to the downfall trend in INV mode. In addition, compared to JL mode, the INV mode exhibits a better negative temperature coefficient of threshold voltage ( $\text{d}V_{\mathrm {th}}$ /dT). Further, the mixed mode circuit simulations are carried out using the Cadence Virtuoso platform through the Verilog-A model. From the analysis, it is observed that an increase of 20% gain in INV mode compared to JL mode for a common source (CS) amplifier. The JL mode NS-FETs achieve higher CMOS inverter switching current ( $I_{SC}$ ) and lower energy-delay products (EDP) as temperature rises. A three-stage ring oscillator (RO) is designed, and the oscillation frequencies ( $f_{\mathrm {OSC}}$ ) of 43.39 GHz and 38.8 GHz are obtained with INV and JL modes. Although JL NS-FET offers less intrinsic capacitances, the $f_{\mathrm {OSC}}$ is high for INV mode due to higher $I_{\mathrm {ON}}$ . Furthermore, reducing supply voltage ( $V_{\mathrm {DD}}$ ), the $f_{\mathrm {OSC}}$ falls by 67% with INV and 62.6% with JL modes. These results will give a better understanding of this emerging NS-FET at both device and circuit levels at advanced technology nodes.

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