Zhejiang Daxue xuebao. Lixue ban (Jul 2024)
Design of CMOS circuit against power analysis attack based on double masked logic(基于双掩码技术的抗功耗攻击CMOS电路设计)
Abstract
To improve the performance against power analysis attacks of the differential pass-transistor pre-charge logic (DP2L) circuit, we proposed a new type of DP2L structure. Compared with the circuit before improvement, the new structure has the same turn-on number of transistors under different input signals, thus showing better performance with constant power consumption. On this basis, the dual-rail double masked differential pass-transistor pre-charge logic (DMDP2L) is further proposed. This structure not only improves the constant power consumption characteristics of the original circuit, but the introduction of double masked technology and the random behavior of the mask increase the difficulty for an attacker to obtain the correct logical values. The results show that the normalized energy deviation (NED) values of the DMDP2L proposed in the paper are reduced by 11.33%, 5.19%, and 3.06%, respectively, compared with those of the same type of circuit in other articles, which indicates that the designed circuit has better characteristics under constant power consumption and better performance against power analysis attacks.(为增强现有差分传输管预充电逻辑(differential pass-transistor pre-charge logic,DP2L)电路结构的抗功耗攻击性能,设计并开发了一种改进型DP2L电路。与改进前电路相比,改进型DP2L电路在不同输入信号下晶体管的导通数目保持相同,从而表现出更好的功耗恒定性能。在此基础上,进一步设计了双轨双掩码差分传输管预充电逻辑(double masked differential pass-transistor pre-charge logic,DMDP2L)电路。该电路不仅改善了原有电路的功耗恒定特性,而且引入的双掩码具有随机性,加大了攻击者获取电路运算结果的难度。模拟结果表明,设计的双轨DMDP2L电路较其他3种同类型逻辑电路的标准化能量偏差(normalized energy deviation,NED)分别减小了11.33%,5.19%和3.06%,表明其具有更好的功耗恒定特性和抗功耗攻击能力。)
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