An Approach to Design a Low Power High-Speed Full Adder Circuit Based on Logical Effort

Abstract

The logical effort method is a technique for accurately estimating the delay of a CMOS circuit. This method is computed as a ratio of capacitances. In this work we propose a low-power full adder circuit and compare it with three established low power full adder circuits. The circuits were designed utilizing Cadence Virtuoso software and GPDK 45nm technology. A comparison was conducted based on delay, average power, power delay product, and transistor count. In this work, all circuits are resized to achieve minimum delay according to the logical effort. It has been shown that the proposed design (design 4) is showing better performance in terms of average power, delay of sum and delay of carry than other designs by 34.23%, 26.81%, and 4.33%, respectively.