Efficient Hardware Implementation of the GOST R 34.10-2001, GOST R 34.10-2012 by FPGA

Abstract

Algorithms of Montgomery multiplication, point’s group operations in Jacobi representation, scalar multiplication are reviewed. The analysis and adaptation of those algorithms for efficient hardware implementation by FPGA consider several features: DSP blocks, possibility of parallel computations. Results of hardware implementation are presented.

Keywords

• digital signature
• GOST R 34.10
• efficient hardware implementation
• Montgomery multiplication
• DSP blocks
• Jacobi representation
• parallel computations