PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits

Abstract

In this paper, the PAELib - an occupied area and power dissipation estimation library written in VHDL - and its use cases are presented. Estimates are based on the structural description of a CMOS digital circuit made with gates/components included in the library; they can be achieved with systematic accounting of leaf components in the structural description. The advantage of this library is that it obtains occupied area and power dissipation estimates using a logic simulator, rather than specialized circuit synthesis or power simulation/estimation software. To validate the library, two use cases are presented. In the first use case, the power dissipation of a 5-stage ring oscillator - implemented with logic gates from the CD4000 series - is estimated and a power estimation error of 16% was obtained. In the second use case, a designer must choose between two implementations of the same finite state machine: one implemented with 74HC series binary counter and the other with D flip flops from the same logic family. The answer is not an obvious one, but the PAElib can offer estimates in an early design stage, allowing the designer to take an informed design decision based on circuit power and area estimates.

Keywords

• logic design
• software libraries
• power dissipation
• logic gates
• CMOS integrated circuits