Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features

Abstract

Hardware Trojans have concealed modifications to integrated circuits (ICs) that can alter their functions, performance, or security properties. Existing Trojan detection methods are designed primarily to detect Trojans at the gate-level IC abstraction and lower levels, and only a few studies have investigated Trojan detection at the register transfer level (RTL). This study presents a novel machine learning-based approach for RTL-level Trojan detection, which leverages conditional statements from Verilog/VHDL code as ML features. Our proposed method has several significant novelties. Firstly, it can detect unknown Trojan instances since we incorporate general features for all Verilog circuits. Second, our approach can detect nontrigger-based Trojans, which are a type of Trojan that is particularly challenging to detect and has not been addressed by many existing techniques. Third, we incorporate feature engineering techniques, including Mutual Information and Person-Coefficient Correlation, to select the best features. We also implement feature scaling with standardization before balancing the data set. Our experimental results demonstrate that our approach achieves an average accuracy of 95.65% in the detection of Trojans, which is higher than previous detection techniques. The method is tested in the Trust-Hub Trojan benchmark RTL design, which demonstrates its effectiveness in detecting a wider range of Trojans at the RTL level. In summary, our novel approach shows great promise for enhancing hardware security by detecting a wider range of Trojans, including previously unseen Trojans, and improving detection&Ahat; accuracy.

Keywords

• Hardware trojan
• RTL
• machine learning
• detection
• Verilog
• VHDL