Synchronisation Strategy in Complex Digital Voter-based Systems

Abstract

Researchers in microelectronics generally agree that reliability and computing power are the two most important factors for next generation digital systems. Redundancy techniques are implemented widely to increase the reliability and fault tolerance of these systems. In this paper a triple modular redundancy (TMR) majority voter based fault-tolerant digital system architecture is presented and analyzed. The vast majority of researchers that design and implement such systems usually assume that in these configurations the voter operates perfectly while is not true. This presentation outlines a specific situation when under same conditions the digital voter is exposed to misleading operation generating wrong information on its output. To overcome such situations there a versatile method has been proposed and implemented that is well suited to overcome the improper operation of TMR structures. The experimental results prove the theoretical assumptions and validate the initial expectations regarding the considered digital system fault-tolerant operation.

Keywords

• digital voter
• reliability
• fault-tolerance
• majority voting
• FPGA processor