Compact software/hardware co-design and implementation method of Aigis-sig digital signature scheme

Abstract

Digital signature scheme Aigis-sig, constructed on ideal lattice, takes the advantages of high efficiency, short signature length and resistant to quantum attack, etc. An optimized modular multiplication arithmetic component was constructed and a compact hardware architecture for polynomial operation over a ring based on number theory transformation (NTT) algorithm for Aigis-sig was designed. Besides, based on this architecture, software/hardware co-design and implementation for Aigis-sig scheme on FPGA platform in cryptography was proposed. Experimental results show that the speed of signature phase and verification phase are increased by about 26% and 17% respectively, compared with the pure software implementation on Xilinx Zynq-7000 SoC platform when CPU clock frequency and hardware clock frequency are set as 666.66MHz and 150 MHz respectively.

Keywords

• post-quantum cryptography
• digital signature
• aigis-sig
• fpga
• number theory transformation