Statistical Timing Analysis for Subthreshold Circuit Based on Bayesian Inference

Abstract

Accurately predicting the delay distribution of subthreshold circuits is crucial for verifying the timing closure of digital circuits and estimating parameter yields. The delay variation, which is the parameter of delay distribution, is not independent of the adjacent cells, because of the input conversion changes caused by the previous gate, making it difficult to model and estimate. The most accurate delay prediction method is Monte Carlo simulation. To obtain accurate estimates, a large number of Monte Carlo simulations are often required, with the consideration of process changes, which is not feasible in large circuits. In this study, a statistical model for path delay that is independent of the cell delay model is proposed. Bayesian inference is used to estimate cell delay with only a small number of Monte Carlo simulations. We then estimated the correlation coefficient of adjacent cells in the path. Finally, the variance and mean of the path delay are calculated using the statistical model proposed above. The results show that using Bayesian inference can accurately estimate the path delay distribution with 100 Monte Carlo simulations as the evidence set where operation voltage is 0.2V to 0.3V. Compared with the traditional 1e5 Monte Carlo simulation method, the speed is about 1000 times faster and the required storage space is reduced by 3 orders of magnitude. In the temperature range of the subthreshold circuits, the error of the delay variance was within 5%, and the error of the delay mean was within 2%.

Keywords

• Subthreshold circuits
• Bayesian inference
• statistical timing analysis