A Parity-Based Dual Modular Redundancy Approach for the Reliability of Data Transmission in Nanosatellite’s Onboard Processing

Abstract

Nanosatellites’ embedded systems must adapt to power, weight, size, and cost constraints. Thus, over the years, the use of Commercial-Off-The-Shelf (COTS) System-on-Chip (SoC) has become common. They have a lower development cost and better performance when compared to components specifically designed for space, although they are more susceptible to the radiation effects. A point of attention in these devices is the reliability of data transmitted between hardcore processors and applications in the reconfigurable logic area. This work proposes a Parity-based Dual Modular Redundancy (PDMR) approach for use in interconnect interfaces of COTS SoCs. The experiments were conducted through simulations with Python scripts and hardware implementations in a Xilinx Zynq-7000 SoC. The proposed technique was compared with the Triple Modular Redundancy (TMR) technique. The simulation results show that for specific rates, the proposed approach reaches values close to those of the TMR and implies a smaller number of bits transmitted even when data detected as erroneous are retransmitted. Meanwhile, hardware implementation results demonstrate a decrease in hardware resource utilization and power consumption compared to TMR implementation.

Keywords

• Nanosatellite
• data transmission
• fault tolerance
• FPGA
• DMR
• parity