HyDra: Hybrid Task Mapping Application Framework for NOC-Based MPSoCs

Abstract

Multiprocessor System-On-Chip (MPSoCs) with Networks-on-Chip (NoCs) has been proposed to address the communication challenges in modern dynamic applications. One of the key aspects of design exploration in NoC-based MPSoC is application mapping, which is critical for the parallel execution of multiple applications. However, mapping for dynamic workloads becomes challenging due to the unpredictable arrival times of applications and the availability of resources. In this work, we propose a hybrid task mapping approach, HyDra, that combines design-time mapping and efficient runtime remapping to reduce communication and energy costs. The proposed approach generates multiple application mappings during the design phase by minimizing latency, energy, and communication costs. The diverse mapping possibilities produced at design time consider multiple performance metrics. However, we cannot predict the arrival time of applications and the availability of resources at design time. To further optimize the MPSoC performance, our dynamic mapping phase re-configures the design time mappings based on the runtime availability of resources and applications. The simulation results show that HyDra reduces communication costs by 14% while using 15% less energy for small and large NoCs compared to state-of-the-art task mapping techniques. Furthermore, our approach provides an average of 19% reduction in end-to-end latency for applications. Our hybrid task allocation and scheduling approach effectively addresses communication issues in NoC-based MPSoCs for dynamic workloads. HyDra achieves improved performance by combining design-time and runtime mapping, providing a promising solution for future MPSoC design.

Keywords

• Hybrid application mapping
• multiprocessors
• network-on-chip
• particle swarm optimization
• simulated annealing
• task graph for free