Proposed work addresses the existing thermal problem of OR-XNOR based circuit by introducing design time thermal management technique at the logic level. The approach is used to reduce the peak temperature by eliminating local hotspots. In proposed thermal-aware synthesis, non-dominated sorting genetic algorithm-II (NSGA-II) based meta-heuristic search algorithm is used to select a suitable input polarity of Mixed Polarity Dual Reed-Muller Expansion (MPDRM) to reduce the power and power-density by optimizing the area sharing. A parallel tabular technique is used for input polarity conversion from Product-of-Sum (POS) to MPDRM function. Finally, the optimized solutions are implemented in the physical design level to obtain the actual values of area, power, and temperature. MCNC benchmark suit is considered for performance evaluation. A comparative study of the proposed approach with existing state-of-art algorithms such as fixed and mixed polarity Reed-Muller network is reported. A significant reduction in area occupancy, power dissipation, and peak temperature generation are reported.