Area and Speed Efficient FPGA Design of S-Box AES-256 Galois Field Approch Based on Logic

Abstract

This paper Provides Compared S-box Galois Field Approach Based on LUT and Logic Gates for AES in terms of decreased chip size and decreased delay, which enhances performance. Data security is a fundamental requirement in the digital age. Modern cryptography encryption techniques are essential for creating secure communication. The Advanced Encryption Satandard (AES) is widely regarded as the cryptography field's strongest encryption technique. The Operate Three Stage Pipeline process to reduce delay of S-box AES-256 using logic gates Galios Field approch. So,accordingly increse speed. Additionally, results of the suggested and existing approaches were compared. The proposed approch simulated and sythesised with Virtex-5 FPGA device along with design in verilog code in xilinx 14.7 software.