Interconnect-Induced Effects on High-Speed Submicron ADC and Clocking Scheme

Abstract

This paper addresses the impact of interconnects imperfections on SNR, INL and DNL of a typical ADC. It is shown that the interconnect-induced jitter reduces SNR up to 25 dB for global interconnects. Considering only the resistance of interconnects, DNL exhibits 3 times dependency more than that of INL. Also a design methodology, based on a stochastic length function, is proposed to find an optimum scheme for clock distribution and to minimize the delay.

Keywords

• Interconnect
• ADC
• Delay
• Clock Distribution