Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and Charging

Abstract

This work presents dynamic state writing by combining ferroelectric (FE) polarization together with charge injection (CI) on Si-based ferroelectric MOSFETs as a novel approach for non-volatile memory design. FE capacitors are non-destructively integrated in the Back-End-of-Line (BEOL) with Si MOSFETs to create FE-Metal-FETs (FeMFETs). We explore the FE/MOS area ratio (AR) as a critical design parameter, particularly in the context of dynamic writing processes, where various voltage pulse trains are applied for analog potentiation and depression of the memory state. AR significantly influences both the electric field distribution over the FE and the extent of CI from the top electrode. Constant-pulse writing schemes enable analog threshold voltage modulation by considering the AR, with reduced voltages and faster operation for smaller ARs. Retention of intermittent states written by FE polarization combined with CI is demonstrated, illustrating the stability and effectiveness of FeMFET devices and AR optimization for memory applications.

Keywords

• BEOL integration
• CMOS
• FeFET
• ferroelectricity
• HZO
• non-volatile memory