FPGA Implementation of Nerve Cell Using Izhikevich Neuronal Model as Spike Generator (SG)

Abstract

The neuron is sometimes referred to as the “head” or “central” cell of the nervous system since it has the ability to communicate with other neurons or cells via electrical impulses. The hardware realization and simulation of these neurons are critical in neuromorphic engineering. In this paper, we made a device that generates 4 different spiking patterns of the nervous system as a Spike Generator (SG) using a hybrid approximation of the target model called the Piece-Wised Power-2 Based Izhikevich Model (PWP2BIM). This proposed model works in a low-cost state to achieve a correct digital implementation of the Izhikevich model, one of the main neuron models (i.e. decreasing hardware resources and enhancing speed and accuracy). The proposed model successfully reproduces the behavioral traits of the initial neuron model. To verify the results of the mathematical simulation, the proposed model was synthesized and implemented on the Zynq XC7Z010 (3CLG400) reconfigurable board (FPGA). The findings of hardware synthesis and applications of the suggested paradigm demonstrate that certain biological behaviors may be duplicated more effectively and at a significantly lower cost. The suggested model’s frequency can be increased using this technique (implemented on the Zynq board) at least by 3.6 times compared to the original model, and power consumption can be decreased by 28%. High-frequency design of neuronal models with low-cost attributes is required for application-based types of equipment in case of high-speed operations of these components. Thus, using our approach, the desired goals of application-based features are to be fulfilled. In addition, because the suggested model uses fewer hardware resources than the original model, it is feasible to construct a significantly higher number of neurons (approximately 5 times) on a single Zynq board.

Keywords

• Izhikevich
• FPGA
• digital FPGA realization
• neuron
• hardware implementation
• low-cost