IMPLEMENTATION OF A VERILOG-BASED DIGITAL RECEIVER FOR 2.4 GHz ZIGBEE APPLICATIONS ON FPGA

Abstract

This paper presents the implementation of a digital receiver for 2.4 GHz Zigbee IEEE 802.15.4 applications on a Spartan3E XC3S500E field programmable gate array (FPGA). The proposed digital receiver comprises an offset quadrature phase shift keying (OQPSK) demodulator, chip synchronization, and a de-spreading block. A new design method that uses Verilog hardware description language (HDL) code through Xilinx ISE version 12 was developed to design these blocks. These blocks were integrated into one top module for optimization. Simulation and measurement were conducted to verify the functionality of the receiver. Implementation results show that the receiver design matched the theoretical expectation. The implementation configuration required up to 22% less slices, flip-flops (FFs), and look-up tables (LUTs) than that in previous research. The clock frequencies used were as low as 250 kHz and 2 MHz.

Keywords

• Verilog
• Digital receiver
• Zigbee
• IEEE 802.15.4 standard
• FPGA