A digital phase‐based on‐fly offset compensation method for decision feedback equalisers

Abstract

Abstract A low‐complexity method to reduce the offset voltage of dynamic comparators employed as samplers in decision feedback equalisers (DFE) is introduced. The authors propose the phase‐domain offset reduction technique (PORT), which leverages an all‐digital phase estimation of output data for offset compensation, without setting the comparator input to a common‐mode voltage (VCM). While traditional techniques might break the data link for offset adjustment, the proposed technique allows calibrating the comparator on‐the‐fly. Measurements from a 26‐dB‐loss on‐chip emulated channel with chip‐scope capability validates PORT through eye‐diagrams at sampler input. A prototype was implemented in a TSMC 130 nm 1.2 V process, and experimental results show the possibility of extending PORT to state‐of‐the‐art technology nodes for multi‐gigabit operation.

Keywords

• calibration
• comparators (circuits)
• decision feedback equalisers
• phase estimation