High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA

Abstract

The paper presents an application of the ASMD-FSMD technique for designing high-performance digital circuits on the example of an implementation of sequential multipliers in reconfigurable FPGA devices. The method primarily enables multiple operations on the same variable within a single clock cycle. The experiments were conducted using the QuartusPrime tool and Cyclone 10 LP devices, as well as Vivado tools and the Kintex UltraScale family device. The bit size of multiplicands varied from 4 to 128. A comparison of the ASMD-FSMD technique with the traditional approach using datapath with the controller has shown that the performance of the sequential multipliers increases by a factor of 2 and, for some examples, by a factor of 3. Practical recommendations for using the ASMD-FSMD technique to improve the performance of digital devices, as well as directions for further studies, are given in the conclusion.

Keywords

• algorithmic state machine with datapath
• finite state machine with datapath
• high-level synthesis
• performance
• FPGA
• Verilog HDL