Generative AI Assertions in UVM-Based System Verilog Functional Verification

Abstract

This paper investigates the potential of leveraging artificial intelligence to automate and optimize the verification process, particularly in generating System Verilog assertions for an Advance Peripheral Bus verification environment using Universal Verification Methodology. Generative artificial intelligence, such as ChatGPT, demonstrated its ability to produce accurate and valuable assertions by employing text-based prompts and image-fed inputs, significantly reducing the required manual effort. This research presents a way of generating System Verilog assertions using the ChatGPT prompt, presenting an image to the Large Language Models, and requesting the assertions needed for the respective protocol. This approach shows the potential for artificial intelligence to revolutionize functional verification by automating complex tasks, ultimately ensuring faster and more reliable System-on-Chip development. The assertions generated by the Large Language Models are integrated into an existing Advance Peripheral Bus verification environment. This process involves running the assertions on a free EDA Playground platform with all three simulators (Cadence Incisive, Mentor Questa, and Synopsys Verilog Compiler Simulator). The main conclusions are that using ChatGPT-4.0 for generating System Verilog assertions significantly reduces the time and effort required for functional verification, demonstrating its potential to enhance efficiency and accuracy in verifying complex System-on-Chip designs.

Keywords

• System Verilog
• ChatGPT
• Universal Verification Methodology
• System-on-Chip
• Large Language Models