Designing efficient QCA even parity generator circuits with power dissipation analysis

Abstract

In the era of modern digital technology, highly scaled and ultra-low power consuming devices have drawn a considerable attention. Quantum-dot Cellular Automata (QCA) are such an emerging nanotechnology that dispenses a highly dense and ultra-low power consuming binary information encoding paradigm. This potential merit instigated the QCA to be an excellent alternative to the conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this paper, we are going to introduce highly scaled and ultra-low power consuming 4, 8, 16 and 32-bit even parity generator circuits. The proposed 4-bit even parity circuit requires 72% fewer cells and occupies 78% less area as compared to previous best designs. Besides, the proposed 32-bit even parity design occupies only 0.283 µm2 whereas the previous best reported design occupies 2.08 µm2 area. The simulation outcomes reveal that our presented designs have considerable enhancements in terms of cell counts, area and power consumption aspects. In addition, to design and verify the proposed layout, QCADesigner is employed and power dissipation is estimated using QCAPro. Keywords: Quantum-dot Cellular Automata, Even parity generator in QCA, Power dissipation, QCADesigner, QCAPro