Modeling and Simulation of Timing Sequence of Distributed Integrated Navigation System Based on 1394 Network

Abstract

To ensure the reliable operation of the bus network for distributed systems, a bus network checking procedure should be made before the operation of the system to eliminate the influence of a faulty node or faulty cables. However, a timing problem may occur during the checking procedure, when the source clock of the bus controller switched. Base on a false alarm during the checking procedure for a distributed integrated navigation system, the author explored the causes and timing sequence of the false alarm by theoretical analysis and simulation. The result shows that the asynchronous clock between the integrated navigation computer and the bus controller causes the software of the integrated navigation computer to read the same cache in DPRAM in two adjacent cycles, which is the root cause of false alarm.

Keywords

• distributed navigation system
• 1394b bus network
• timing sequence and simulation