A joint design method of frame synchronization code and LDPC code

Abstract

Frame synchronization word (FSW) is an important basis in signal synchronization detection. In our work, the joint design of frame synchronization words and error correcting code are proposed which through regularly distributing the frame synchronization words among the information bits to improve the decoding performance of the LDPC. Frame synchronization word should be added to the information sequence corresponding to the position with the check matrix larger column weight which can guarantee that more Frame synchronization words are received by the check node in the decoding iteration. The frame synchronization word is known to the receiver which play an important role in decoding iteration. The results of simulation show that the algorithm makes an obvious improvement in decoding performance when the signal-noise ratio (SNR) is lower than 1 dB.