Design Considerations for Integrated Radar Chirp Synthesizers

Abstract

Phase-locked loops (PLLs) effectively generate frequency chirps for frequency-modulated continuous-wave (FMCW) radar and are ideal for integrated circuit implementations. This paper discusses the design requirements for integrated PLLs used as chirp synthesizers for FMCW radar and focuses on an analysis of the radar performance based on the PLL configuration. The fundamental principles of the FMCW radar are reviewed, and the importance of low synthesizer phase noise for reliable target detection is quantified. This paper provides guidance for the design of chirp synthesizer PLLs by analyzing the impact of the PLL configuration on the accuracy and reliability of the radar. The presented analysis approach allows for a straightforward study of the radar performance and quantifies the optimal settings of a PLL-based chirp synthesizer for a given application scenario, while the developed methodology can be easily applied to other scenarios. A novel digital chirp synthesizer PLL design that meets the requirements of FMCW radar is presented. The synthesizer prototype fabricated in 65-nm CMOS drives a radar testbed to verify the effectiveness of the synthesizer design in a complete FMCW radar system.

Keywords

• Chirp linearity
• chirp synthesis
• frequency-modulated continuous-wave (FMCW) radar
• fully-integrated chirp synthesizer
• phase locked loop (PLL)
• phase noise