Improved simulation modelling and its verification for SiC MOSFET

Abstract

Abstract Of crucial importance is to accurately simulate its switching characteristics for the application of SiC MOSFET. Due to the ultrafast switching capability, SiC MOSFET is dependent on interelectrode capacitances and extremely sensitive to parasitics. Therefore, accurate modelling of interelectrode capacitances and knowledge of parasitics are required. Here, an improved SiC MOSFET model driven by an empirical formula with three segments for the non‐linear drain‐to‐gate capacitance in relationship with the drain‐to‐source voltage is developed. In this way, the capacitance fitting at the inflection point that has a great impact on the switching delay is much improved. By simple self‐made high‐voltage C–V measurement systems, the accuracy of the proposed formula is verified. More importantly, intruded parasitics by the commonly‐used coaxial shunt current measurement loop is analysed in detail. The equivalent circuit of the current measurement loop is incorporated into the device simulation circuit to compensate measurement errors. In this way, the improved model can be more reliably verified and evaluated. A double pulse test is built to verify the proposed model. By comparison of simulation and experimental results, the proposed model works well at different voltage and current operating conditions and offers a reliable and accurate modelling approach.