A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting

Abstract

This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phase-shifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the feedback and reference signals becomes sufficiently small. Then, a toggling phase-shifting in the second stage achieves further reduction of the phase offset by delaying the feedback and reference signals. A subsequent adaptive target index-shifting stage then detects fine-locking in frequency and rapidly performs phase-locking to the present phase of the feedback signal instead of the initial target phase. This TSPS-ADPLL avoids frequency peaking by choosing oscillator control codes that generate frequencies below or near the target. Fabricated in a 28nm CMOS process, this ADPLL can lock within $1.0~\mu \text{s}$ , producing a 2.4GHz output clock without frequency peaking. It has an RMS jitter of 2.53ps and draws 2.89mW from a 1.0V supply.

Keywords

• Fast-locking
• phase-shifting
• frequency peaking
• frequency search
• digital clock generator
• all-digital phase-locked loop (ADPLL)