Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell

Abstract

Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems. This work proposes a novel Carbon nanotube field-effect transistor (CNTFET) in designing a robust memory cell to overcome these soft errors. Further, a petite driver circuit to test the SRAM cells which serve the purpose of precharge and sense amplifier, and has a reduction in threefold of transistor count is recommended. Additionally, analysis of robustness against radiation in varying memory cells is carried out using standard GPDK 90 nm, GPDK 45 nm, and 14 nm CNTFET. The reliability of memory cells depends on the critical charge of a device, and it is tested by striking an equivalent current charge of the cosmic ray’s linear energy transfer (LET) level. Also, the robustness of the memory cell is tested against the variation in process, voltage and temperature. Though CNTFET surges with high power consumption, it exhibits better noise margin and depleted access time. GPDK 45 nm has an average of 40% increase in SNM and 93% reduction of power compared to the 14 nm CNTFET with 96% of surge in write access time. Thus, the conventional MOSFET’s 45 nm node outperforms all the configurations in terms of static noise margin, power, and read delay which swaps with increased write access time.

Keywords

• soft errors
• CNTFET
• linear energy transfer
• static noise margin