The design and implementation of SpaceWire high speed bus interface controller

Abstract

In view of the requirement of high-speed transmission of payload data in space application, a design scheme of SpaceWire interface controller is proposed according to the SpaceWire protocol. The logic is designed by Verilog programming language, and the interface controller IP is implemented. The prototype is verified by XC4VSX55 FPGA, and the feasibility of the whole design is verified. The IP is implemented in the ASIC LoongSon 1E300. The testing environment is setup, and the synchronization and accuracy of the data transmission process is verified. The actual test results of the ASIC show that the interface′s signaling rates can reach 200 Mb/s, which satisfies the functions stipulated by the protocol.

Keywords

• SpaceWire
• interface controller
• Codec
• high-speed data transmission