A 3.7-mW 12.5-MHz 81-dB SNDR 4th-Order Continuous-Time DSM With Single-OTA and 2nd-Order Noise-Shaping SAR

Wei Shi; Jiaxin Liu; Abhishek Mukherjee; Xiangxing Yang; Xiyuan Tang; Linxiao Shen; Wenda Zhao; Nan Sun

doi:10.1109/OJSSCS.2022.3212333

IEEE Open Journal of the Solid-State Circuits Society (Jan 2022)

A 3.7-mW 12.5-MHz 81-dB SNDR 4th-Order Continuous-Time DSM With Single-OTA and 2nd-Order Noise-Shaping SAR

Wei Shi,
Jiaxin Liu,
Abhishek Mukherjee,
Xiangxing Yang,
Xiyuan Tang,
Linxiao Shen,
Wenda Zhao,
Nan Sun

Affiliations

Wei Shi: ORCiD; Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA
Jiaxin Liu: ORCiD; Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China, Chengdu, China
Abhishek Mukherjee: ORCiD; Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA
Xiangxing Yang: ORCiD; Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA
Xiyuan Tang: ORCiD; Institute for Artificial Intelligence and School of Integrated Circuit, Peking University, Beijing, China
Linxiao Shen: ORCiD; School of Integrated Circuit, Peking University, Beijing, China
Wenda Zhao: ORCiD; Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA
Nan Sun: Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA

DOI: https://doi.org/10.1109/OJSSCS.2022.3212333
Journal volume & issue: Vol. 2
pp. 122 – 134

Abstract

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This article presents a hybrid 4th-order delta–sigma modulator (DSM). It combines a continuous-time (CT) loop filter and a discrete-time (DT) passive 2nd-order noise-shaping SAR (NS-SAR). Since the 2nd-order NS-SAR is robust against PVT variation, the stability of this 4th-order DSM is similar to that of a 2nd-order CT-DSM. The CT loop filter is based on single-amplifier–biquad (SAB) structure. As a result, only one OTA is used to achieve 4th-order noise shaping, leading to a high power efficiency. Moreover, this work implements both excess-loop delay (ELD) compensation and an input feedforward path inside the NS-SAR in the charge domain, further reducing the circuit complexity and the OTA power. Overall, this work achieves 81-dB SNDR over 12.5 MHz with 3.7-mW power, leading to a Schreier FoM of 176 dB.

Published in IEEE Open Journal of the Solid-State Circuits Society

ISSN: 2644-1349 (Online)
Publisher: IEEE
Country of publisher: United States
LCC subjects: Technology: Electrical engineering. Electronics. Nuclear engineering: Electric apparatus and materials. Electric circuits. Electric networks
Website: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8782712

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