An Area-Efficient TMR Architecture Inspired From Fast FIR Algorithm for Fault Tolerance

Abstract

High-end commercial silicon chips used in aerospace and other industries utilize technology nodes at deep sub-micron levels. Efforts are underway to assess the feasibility of integrating even smaller nano-scale devices for secure communication, high-speed computing, and data storage. Due to radiation impacts, these nanoscale technologies are susceptible to both temporary and permanent errors. Various mitigation techniques have been employed to address these errors, Triple Modular Redundancy (TMR) being the most widely used, despite its 200% area overhead (without the voter block). Digital FIR filtering is a versatile tool with a wide range of applications in RADAR signal processing, telecommunication systems, image and speech processing, and fault-tolerant FIR filters (FTFIR) are crucial for some applications. This work proposes an area-efficient TMR architecture based on a fast 3-parallel FIR structure. Instead of the default TMR approach of triplicating the FIR filters, a polyphase-decomposed parallel fast FIR filter algorithm (FFA) is used. This three-parallel structure reduces hardware requirements hence area, and enhances performance. Compared to conventional TMR designs, the proposed fast 3-parallel architecture implemented in 45nm technology with a matching voter is more efficient, saving 51% of the area and 77% of the power.

Keywords

• Fault tolerant systems
• FIR filters
• fast FIR algorithm (FFA)
• parallel FIR filter
• TMR