A high linearity LNA for low voltage GPS receiver

Abstract

Based on 0.18 μm RFCMOS technology, a high linearity low noise amplifier(LNA) for low voltage GPS receivers was designed. By using the trans-conductance derivative superposition technique with bulk bias control, the adjustment accuracy of auxiliary transistor was remarkably improved. An extra capacitance is added between gate and source nodes of input transistor in a parallel manner to reduce the effect of second-order harmonic on IMD3. In addition, folded cascade structure is adopted to make the circuit work under low voltage conditions. The simulation results shown that the LNA achieves a 6.63 dBm IIP3, a noise figure of 1.53 dB, a 13.16 dB power gain, the input and output return losses are -32.43 dB and -24.58 dB at 1.575 GHz with the core LNA consuming 8.78 mW at 0.9 V power supply.

Keywords

• high linearity
• lna
• trans-conductance derivative superposition technique