Embeddable parallel digital image of doubly-fed induction generator

Abstract

Due to the complexity of the structure of doubly-fed induction generator (DFIG), it is difficult to conduct real-time simulation. For this reason, this paper designs an embeddable parallel digital image IP of DFIG based on field programmable logic array (FPGA) to realize efficient electromagnetic simulation of DFIG. First, this paper proposes a virtual capacitor equivalent method for induction machine equivalent “T” circuit decoupling; Secondly, based on the principle of data independence and parallelism within the time step, a parallel algorithm for the internal components of DFIG is proposed; Finally, the FPGA-DFIG digital image constructed in this paper is connected to the RT-LAB/power grid, and hardware experiments are carried out under three working conditions: steady state, voltage sag and DC side fault. The experimental results are compared with the simulation results of DFIG grid connected system built in MATLAB/Simulink environment to verify the effectiveness and rapidity of the methods and models proposed in this paper.

Keywords

• FPGA
• Virtual capacitor equivalent method
• Parallel computing
• DFIG
• Faster-than-real-time simulation