DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors

Abstract

Grain boundary (GB) at the source/drain (S/D) epitaxy was investigated using fully-calibrated TCAD. Because the S/D epi is grown separately at the bottom and the NS channels, nanosheet field-effect transistors (NSFETs) have unwanted GB within the S/D epi which fully relaxes the channel stresses. This GB changes the doping profiles and the stress values, which thus degrade the DC performances. We focused on single GB with different inclined angles and positions. N-type NSFETs have similar DC performances regardless of the GB since the changes of doping and stress were small. P-type NSFETs suffer from DC performance degradations but different depending on the GB positions. As the GB splits the p-type S/D epi into two, lower S/D below the GB has tensile stress and upper S/D above the GB has compressive stress. Since tensile stress increases boron diffusivity, more boron dopants diffuse into the NS channels as the device has lower S/D region, thus suffering the short channel effects greatly. The device having upper S/D region loses the channel stress much, so it degrades the on-state performance. This study provides clear understanding of the GB effects of NSFETs.

Keywords

• Grain boundary
• nanosheet
• doping
• stress
• DC performance
• short-channel effect