Migration in Hardware Transactional Memory on Asymmetric Multiprocessor

Abstract

In this paper, a system is presented which implements transactions migration to an asymmetric multiprocessor in order to decrease the probability of conflicts and improve execution performance. Applications parallelization makes programming and testing much more difficult, so the goal is to avoid putting additional burden on a programmer. Therefore, the proposed solution should be fully implemented in hardware. In the asymmetric multiprocessor that is analyzed, all cores have the same instruction set, but they are asymmetric in terms of microarchitectural properties, so that N −1 “small” cores are identical, while the $\text{N}^{\mathrm {th}}$ “big” core is different, as it provides better performance and higher capacities of its units. The idea is to perform transaction migration from the “small” core to the “big” one, based on the history of transaction execution. The experiments were performed using a significantly upgraded Gem5 simulator and eight parallel applications from the STAMP benchmark suite. The experimental results show the speedup and the rate of successfully executed transactions for five different multiprocessor configurations, including symmetric and asymmetric multiprocessors with or without transaction migration. The improvement our algorithm achieves for suitable applications is up to 14% (10% on average) in turnaround time compared to the solutions which do not make use of asymmetry for scheduling transactions.

Keywords

• Shared memory algorithms
• multicore architectures
• hardware transactional memory
• asymmetric multiprocessor
• thread migration