Modeling and Performance Analysis of Shielded Differential Annular Through-Silicon Via (SD-ATSV) for 3-D ICs

Abstract

A shielded-differential annular through-silicon via (SD-ATSV) is proposed and investigated. The equivalent circuit model is developed with the influence of the electrically floating silicon substrate taken into account. By virtue of the circuit model, the frequency- and time-domain electrical characterizations of the SD-ATSV are conducted. Furthermore, the thermo-mechanical stress of the SD-ATSV is captured and compared with that of the shielded-differential cylindrical through-silicon via. It is demonstrated that by utilizing the SD-ATSV, the keep-out zone can be reduced without performance degradation.

Keywords

• Shielded differential annular through-silicon via (SD-ATSV)
• MOS capacitance
• floating silicon substrate
• thermal stress
• keep-out zone (KOZ)