Charge-parity switching effects and optimisation of transmon-qubit design parameters

Abstract

Abstract Enhancing the performance of noisy quantum processors requires improving our understanding of error mechanisms and the ways to overcome them. A judicious selection of qubit design parameters plays a pivotal role in improving the performance of quantum processors. In this study, we identify optimal ranges for qubit design parameters, grounded in comprehensive noise modeling. To this end, we also analyze the effect of a charge-parity switch caused by quasiparticles on a two-qubit gate. Due to the utilization of the second excited state of a transmon, where the charge dispersion is significantly larger, a charge-parity switch will affect the conditional phase of the two-qubit gate. We derive an analytical expression for the infidelity of a diabatic controlled-Z gate and see effects of similar magnitude in adiabatic controlled-phase gates in the tunable coupler architecture. Moreover, we show that the effect of a charge-parity switch can be the dominant quasiparticle-related error source of a two-qubit gate. We also demonstrate that charge-parity switches induce a residual longitudinal interaction between qubits in a tunable-coupler circuit. Furthermore, we introduce a performance metric for quantum circuit execution, encompassing the fidelity and number of single- and two-qubit gates in an algorithm, as well as the state preparation fidelity. This comprehensive metric, coupled with a detailed noise model, enables us to determine an optimal range for the qubit design parameters, as confirmed by numerical simulation. Our systematic analysis offers insights and serves as a guiding framework for the development of the next generation of transmon-based quantum processors.