An all-digital phase-locked loop based on variable phase accumulator

Abstract

This paper presents a novel all-digital phase-locked loop with variable phase accumulator circuit structure. The design of the system is completed by using EDA technology, and the system simulation experiment is carried out by using ModelSim software, and the hardware experiment is carried out. The experimental results show that the all-digital PLL with variable phase accumulator can extend the phase-locked range of the system loop, increase the frequency of PLL,reduce the total power consumption of the system, and do not increase the logic resources in the FPGA chip. Because the internal signal of the PLL is transmitted in parallel,the speed of PLL can be greatly improved. The PLL can be embedded into an electronic system chip as a functional module, and can be widely used in communication, electronic measurement and automatic control.

Keywords

• all digital phase-locked loop
• variable phase accumulator
• electronic design automation
• computer simulation