Minimum signed digit approximation for faster and more efficient convolutional neural network computation on embedded devices

Abstract

In the era of smart Internet-of-Things, convolutional neural network (CNN) models with low computational overhead are crucial for low-latency applications in resource-constrained embedded devices. The performance and efficiency of multiplication operations play a vital role in accelerating and optimizing CNN computation. In this article, we propose the MA4C technique, which reduces CNN computation overhead by converting a pretrained CNN’s parameters into approximated minimum signed digit (MSD) representations. MSD representation contains fewer non-zero digits on average compared to the binary representation of a number. The proposed scheme approximates the MSD representations by only considering a specified number of most significant digits. The MA4C technique reduces the computational complexity of multipliers by reducing the number of partial sums. The proposed MSD approximation was applied on various DNN models, and their performance was analyzed for different datasets, varying CNN depth, and network configuration. Implementation of our proposed method on FPGA reduced the logic circuits and multiplier latency by up to 4.2× and 1.2× respectively compared to an 8-bit Booth multiplier for most CNN models.

Keywords

• Convolutional neural network
• Accelerator
• Approximate computing
• Signed digit computation
• Low-complexity multiplier