Switchable‐Memory Operation of Silicon Nanowire Transistor

Abstract

Abstract The switchable‐memory operation of a feedback silicon nanowire transistor with a dual‐gate structure is demonstrated. The single transistor exhibits volatile memory characteristics with a retention time longer than 3600 s, as well as a switching capability with a subthreshold swing lower than 7 mV dec−1. A gate‐controlled memory window forms around a gate voltage of 0 V owing to the positive feedback loop in the channel region, allowing a program/erase endurance of more than 1000 cycles. The memory transistor, with switching capability, opens up the possibility of overcoming not only the scaling limit faced by conventional volatile memory but also the inherent drawback of the separation of the building blocks for memory and logic.

Keywords

• one transistor
• positive feedback loop
• silicon nanowires
• switchable‐memory