Variation-resilient spike-timing-dependent plasticity in memristors using bursting neuron circuit

Abstract

Spike-timing-dependent plasticity (STDP) is a classic synaptic function that facilitates learning and memory in a biological brain. Hardware implementation of neural circuits supporting dynamical STDP functions offers notable advantages in terms of processing speed and efficiency over software-based approaches. However, the validity of STDP builds on precise timing of pre- and post-synaptic spikes, while the appearance of intrinsic variations in the analog circuits causes notable distortions to the spike generation and thus affects the learning performance. In this work, we studied the robustness of STDP learning based on responses of a Ta _2 O _5 based memristor and spike inputs from CMOS based neuron circuit. Our simulation showed that circuit-level variations in a leaky-integrate-and-fire (LIF) neuron produced uncontrollable STDP responses and poor training results, severely limiting its feasibility in practical applications. To address this challenge, a high-order neuron capable of burst coding was designed to demonstrate significant improvement in resilience to circuit variations, achieving 93.2% accuracy in STDP-based unsupervised learning tasks, which is notably improved compared to the LIF-based neuron circuit at 88.0%. Our work established a practical solution to mitigate circuit variations in STDP-based learning tasks and paved the way to building large-scale and functional neuromorphic systems with dynamical network behaviours.

Keywords

• neuron circuits
• spike-timing-dependent plasticity
• spiking neural network
• bursting
• memristor