A 13-Bit 100 kS/s Two-Step Single-Slope ADC for a 64 × 64 Infrared Image Sensor

Abstract

An Analog-to-Digital Converter (ADC) is an indispensable part of image sensor systems. This paper presents a silicon-based 13-bit 100 kS/s two-step single-slope analog-to-digital converter (TS-SS ADC) for infrared image sensors with a frame rate of 100 Hz. For the charge leakage and offset voltage issues inherent in conventional TS-SS ADC, a four-terminal comparator was employed to resolve the fine ramp voltage offset caused by charge redistribution in storage and parasitic capacitors. In addition, a current-steering digital-to-analog converter (DAC) was adopted to calibrate the voltage reference of the dynamic comparator and mitigate differential nonlinearity (DNL)/integral nonlinearity (INL). To eliminate quantization dead zones, a 1-bit redundancy was incorporated into the fine quantization circuit. Finally, the quantization scheme consisted of 7-bit coarse quantization followed by 7-bit fine quantization. The ADC was implemented using an SMIC 55 nm processSemiconductor Manufacturing International Corporation, Shanghai, China. The post-simulation results show that when the power supply is 3.3 V, the ADC achieves a quantization range of 1.3 V–3 V. Operating at a 100 kS/s sampling rate, the proposed ADC exhibits an effective number of bits (ENOBs) of 11.86, a spurious-free dynamic range (SFDR) of 97.45 dB, and a signal-to-noise-and-distortion ratio (SNDR) of 73.13 dB. The power consumption of the ADC was 22.18 mW.

Keywords

• TS-SS ADC
• infrared image sensors
• four-terminal comparator
• current-steering DAC
• voltage offset