IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (Jan 2020)
Benchmarking and Optimization of Spintronic Memory Arrays
Abstract
In this article, we present a cross-layer optimization and benchmarking of various spintronic memory devices, including spin-transfer-torque magnetic random access memory (STT-MRAM), spin-orbit-torque (SOT) MRAM, voltage-controlled exchange coupling (VCEC) MRAM, and magnetoelectric (ME) MRAM. Various material, device, and circuit parameters are optimized to maximize array-level READ and WRITE performances and to benchmark spintronic devices against static random access memory (SRAM). It is shown that the optimized parameters, such as magnetic tunnel junction (MTJ) oxide thickness or transistor size, are quite different for various device options. The optimal oxide thickness of VCEC-MRAM is 1.6 nm because it is a voltage-controlled device; thus, thicker oxide gives smaller READ energy-delay product (EDP), whereas, for STT-MRAM, the optimal oxide thickness is 1.3 nm to keep the WRITE voltage low while avoiding READ disturbs. In addition, we find that the co-optimization of material, device, and circuit analyses are critical because it is not enough to identify the most promising material for various device options with only material- or device-level metrics. For instance, SOT materials with the highest spin conductivity may not result in the best array-level WRITE performance because of their large resistivity and, in some cases, READ disturb issues. We also present a new design and cell layout for ME-MRAM in which the number of access transistors depends on the WRITE voltage. The benchmarking results show that SOT-MRAM can be fast and low energy but would suffer from a 25% larger cell area compared with STT-MRAM. VCEC-MRAM can be denser than STT-MRAM (2T1MTJ) and dissipate less energy but would suffer from slower READ operations because of its large oxide thickness. ME-MRAM can be fast, low energy, and dense compared with all other options.
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