Micromachines (Nov 2021)

New Submicron Low Gate Leakage In<sub>0.52</sub>Al<sub>0.48</sub>As-In<sub>0.7</sub>Ga<sub>0.3</sub>As pHEMT for Low-Noise Applications

  • Mohamed Fauzi Packeer Mohamed,
  • Mohamad Faiz Mohamed Omar,
  • Muhammad Firdaus Akbar Jalaludin Khan,
  • Nor Azlin Ghazali,
  • Mohd Hendra Hairi,
  • Shaili Falina,
  • Mohd Syamsul Nasyriq Samsol Baharin

DOI
https://doi.org/10.3390/mi12121497
Journal volume & issue
Vol. 12, no. 12
p. 1497

Abstract

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Conventional pseudomorphic high electron mobility transistor (pHEMTs) with lattice-matched InGaAs/InAlAs/InP structures exhibit high mobility and saturation velocity and are hence attractive for the fabrication of three-terminal low-noise and high-frequency devices, which operate at room temperature. The major drawbacks of conventional pHEMT devices are the very low breakdown voltage (xGa(1−x)As (x = 0.53 or 0.7) channel material plus the contribution of other parts of the epitaxial structure. The capability to achieve higher frequency operation is also hindered in conventional InGaAs/InAlAs/InP pHEMTs, due to the standard 1 μm flat gate length technology used. A key challenge in solving these issues is the optimization of the InGaAs/InAlAs epilayer structure through band gap engineering. A related challenge is the fabrication of submicron gate length devices using I-line optical lithography, which is more cost-effective, compared to the use of e-Beam lithography. The main goal for this research involves a radical departure from the conventional InGaAs/InAlAs/InP pHEMT structures by designing new and advanced epilayer structures, which significantly improves the performance of conventional low-noise pHEMT devices and at the same time preserves the radio frequency (RF) characteristics. The optimization of the submicron T-gate length process is performed by introducing a new technique to further scale down the bottom gate opening. The outstanding achievements of the new design approach are 90% less gate current leakage and 70% improvement in breakdown voltage, compared with the conventional design. Furthermore, the submicron T-gate length process also shows an increase of about 58% and 33% in fT and fmax, respectively, compared to the conventional 1 μm gate length process. Consequently, the remarkable performance of this new design structure, together with a submicron gate length facilitatesthe implementation of excellent low-noise applications.

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