Design and analysis of 32 bit CMOS adder using sub-threshold voltage at deep submicron technology

Abstract

FA is basic cell for arithmetic operation and lots of efforts have put to minimize power consumption and delay. This paper evaluates conventional CMOS adder, bridge style adders in sub-threshold region. Circuits are designed at 20 MHz and 50 MHz frequencies with VDD= 200 mv. All adder designs are simulated at 32 nm technology. In 1 bit and 32 bit conventional CMOS adder design, an efficient trade-off between delay and power is achieved. Experimental results show that 32 bit adder designs have significant improvements in delay and power delay product.