Design of clock control block for DFT

Abstract

DFT is a technique that converts the design into testable after manufacturing. As technology is shrinking, the complexity of inserting the DFT is becoming high. When it comes to DFT timing, controlling clocks in test mode is become a challenge nowadays. To achieve the high scan shift speed and to reduce the tester time, a new architecture is proposed in this work. The objective of this work is to propose a new design for clock controlling in DFT timing and working of the proposed block by configuring the different Test Data Registers. The proposed clock provides the clock intercepts for scan and debug modes along with features such as a single clock entry point per tile, clock stop using TDR, capture clock path same as functional mode path, and staggering pulse generation for LOS and LOC. The scannable logic in any tile must receive a clock from the clock control block. The tile level clock can be gated inside this block. A pulse generation logic is used to control the Gater inside the proposed design. The dynamic power consumption of the proposed architecture is compared with different clock architectures. The dynamic Power consumption is calculated as 60 mW which is less compared to already existing on-chip clock controllers in the DFT.

Keywords

• Design for testability
• Clock control
• Test data register
• Launch on capture
• Launch on shift
• Dynamic power