A Real-Number SNP Circuit for the Adder and Subtractor with Astrocyte-like Dendrite Selection Behavior Based on Colored Spikes
Tonatiuh Jimenez-Borgonio,
Juan Carlos Sanchez-Garcia,
Luis Olvera-Martinez,
Manuel Cedillo-Hernandez,
Carlos Diaz-Rodriguez,
Thania Frias-Carmona
Affiliations
Tonatiuh Jimenez-Borgonio
Instituto Politecnico Nacional, Escuela Superior de Ingenieria Mecanica y Electrica Unidad Culhuacan, Avenida Santa Ana 1000, San Francisco Culhuacan, Culhuacan CTM V, Coyoacan, Ciudad de Mexico CP 04440, Mexico
Juan Carlos Sanchez-Garcia
Instituto Politecnico Nacional, Escuela Superior de Ingenieria Mecanica y Electrica Unidad Culhuacan, Avenida Santa Ana 1000, San Francisco Culhuacan, Culhuacan CTM V, Coyoacan, Ciudad de Mexico CP 04440, Mexico
Luis Olvera-Martinez
Instituto Politecnico Nacional, Escuela Superior de Ingenieria Mecanica y Electrica Unidad Culhuacan, Avenida Santa Ana 1000, San Francisco Culhuacan, Culhuacan CTM V, Coyoacan, Ciudad de Mexico CP 04440, Mexico
Manuel Cedillo-Hernandez
Instituto Politecnico Nacional, Escuela Superior de Ingenieria Mecanica y Electrica Unidad Culhuacan, Avenida Santa Ana 1000, San Francisco Culhuacan, Culhuacan CTM V, Coyoacan, Ciudad de Mexico CP 04440, Mexico
Carlos Diaz-Rodriguez
Independent Researcher, Ciudad de Mexico CP 04440, Mexico
Thania Frias-Carmona
Independent Researcher, Ciudad de Mexico CP 04440, Mexico
In recent years, several proposals have emerged for executing arithmetic operations using different variants of Spiking Neural P (SNP) systems. However, some of these proposals rely on distinct circuits for each arithmetic operation, while others mandate preliminary configurations for result computation. Recent research suggests that the biological brain decides to activate or inhibit specific neurons based on the operations performed, without prior preparation. Building upon this understanding, the current work introduces a real-number arithmetic SNP circuit capable of dynamically adjusting its behavior without the need for prior configuration. This adaptability is achieved by selecting between addition or subtraction through the utilization of astrocyte-like control and colored spikes. To validate its performance, the circuit was implemented on an FPGA system. The results indicate that the growth in the quantity of 10th-order digits is comparable to recent proposals in terms of hardware usage, requiring fewer neurons than alternative approaches. Moreover, the computation of floating-point numbers enhances the resolution and precision in various arithmetic applications.