Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)

Abstract

The high data throughput and high energy efficiency required recently are increasingly difficult to implement due to the von Neumann bottleneck. As a way to overcome this, Logic-in-Memory (LiM) technology has recently been receiving a lot of attention. In particular, since the addition function is important to solve high data throughput in applications such as artificial intelligence, the results of applying various fine-grain LiM application devices to full adder circuit design are being announced. In this paper, a Floating Gate Field Effect Transistor (FGFET), which has a structure similar to a floating gate memory cell transistor that has been widely used in the past and is highly applicable to mass production, was applied to the LiM application circuit design. Prior to application to circuit design, the FGFET characteristics were confirmed using a well-calibrated technology computer-aided design (TCAD) simulation at the 32nm technology node, and a compact model was developed to describe them. Afterwards, the delay and power consumption were evaluated with three different types of FGFET-based full adder circuits, and benchmarked with conventional CMOS (complementary metal-oxide-semiconductor)-based conventional full adder circuits.

Keywords

• von Neumann bottleneck
• logic-in-memory
• floating gate field effect transistor (FGFET)
• full adder
• compact modeling